DIPS-V20

In the fall of 1981, a plan was formulated to develop a basic model of a small DIPS processor (the DIPS-V20). The goals of this plan included expanding application of DIPS to small-scale areas and developing applications to network internal communications processing; work was begun to make the technologies practical. The main points of the plan were a dual multiprocessor configuration, approximately 1/3 the performance of the DIPS-11 Model 5, 8-MB memory capacity, connection of small low-cost peripheral devices, and communications capability based on the data flow communications control (DFC) system.