Hitachi HITAC 5020

This was a large general-purpose electronic computer, developed based on Hitachi's own technology. It was designed and manufactured primarily for calculations relating to science/engineering or scientific management, but it was also appropriate for business calculations. In April 1960, Kenro Murata and Kisaburo Nakazawa-- the leading designers of TAC, the University of Tokyo's vacuum tube based computer -- joined Hitachi Ltd., and development of the HITAC 5020 began. The instruction system of the HITAC 5020 was based on the "FABM" concept (where F stands for Function, A for A-reg (accumulator), B for B-reg (index register) and M for memory), and the idea was to handle A, B and M in a uniform fashion. That is, the idea was for both the A and B registers to be the same, and for addresses 0-15 to have addresses as memory. Studies began on basic circuits in July 1960, in parallel with system design, and in December, it was decided to use a system with diode logic, emitter/follower and current switching type regenerative amplifiers, and there were good prospects of achieving operation at 18MHz using the dot-mesa type HS-510.