Dr. Joseph (Josh) A. Fisher

An American computer scientist noted for his work on VLIW architectures, compiling, and instruction-level parallelism, and for the founding of Multiflow Computer. He is a Hewlett-Packard Senior Fellow (Emeritus). He received his B.A. degree in Mathematics in 1964 (with honors) from New York University, and his Master's degree and Ph.D. in 1979; both in Computer Science from The Courant Institute of Mathematics of New York University. In his Ph.D. dissertation, he created the Trace Scheduling compiler algorithm and coined the term Instruction-level parallelism to characterize VLIW, superscalar, dataflow and other architecture styles that involve fine-grained parallelism among simple machine-level instructions. Trace scheduling was the first practical algorithm to find large amounts of parallelism between instructions that occupied different basic blocks. This greatly increased the potential speed-up for instruction-level parallel architectures. Because of the difficulty of applying trace scheduling to idiosyncratic systems (such as 1970s-era DSPs) that in theory should have been suitable targets for a trace scheduling compiler, he put forward the VLIW architectural style. VLIWs are normal computers, designed to run compiled code and used like ordinary computers, but offering large amounts of instruction-level parallelism scheduled by a trace scheduling or similar compiler. VLIWs are now used extensively, especially in embedded systems. The most popular VLIW cores have sold in quantities of several billion processors. He joined the Yale University Department of Computer Science in 1979 as an Assistant Professor, and was promoted to Associate Professor in 1983. In April, 1984 he left Yale to found Multiflow Computer, Inc. with Yale colleagues John O'Donnell and John Ruttenberg. Multiflow was founded to commercialize trace scheduling and VLIW architectures, (at that time widely thought to be impractical). It was a manufacturer and seller of minisupercomputer hardware and software embodying the VLIW design style. Multiflow's technical success and the dissemination of its technology and people had a great effect on the future of computer science and the computer industry. Multiflow ended operations on March 27, 1990, two days after a large deal contemplated with Digital Equipment Corporation came apart. At that point, the board determined that the prospects for successful additional financing, in the amounts necessary to bring Multiflow to maturity, were too unlikely to justify the company?s continuation. Upon the closing of Multiflow, he joined HP Laboratories in Palo Alto, California, the exploratory and advanced research group for Hewlett-Packard. He directed HP Labs in Cambridge, Massachusetts from its founding in 1994, and became an HP Fellow in2000; and then Senior Fellow in 2002 upon the inception of those titles at Hewlett-Packard. He retired from HP Labs in 2006. He has been the recipient of several awards and honors to include ? the 1984 NSF Presidential Young Investigator's Award. (This award was meant to persuade promising faculty to stay at universities; financial grant to Yale University declined due to his leaving to start Multiflow). In 1987 he received the Eli Whitney Connecticut Entrepreneur of the Year; and in 2003, the Eckert-Mauchly Award given by The IEEE Computer Society and The Association for Computing Machinery, ?in recognition of 25 years of seminal contributions to instruction-level parallelism, pioneering work on VLIW architectures, and the formulation of the Trace Scheduling compilation technique?. The Eckert-Mauchly is known as the computer architecture community?s highest award. In 2012 he received the B. Ramakrishna Rau Award; also given by The IEEE Computer Society, ?for the development of trace scheduling compilation and pioneering work in VLIW (Very Long Instruction Word) architectures?. Among the publications he has authored or co-authored are: ?Trace Scheduling: A Technique for Global Microcode Compaction? IEEE Trans. Computers, 30(7):478-490, 1981; with B. Ramakrishna Rau, ?Instruction-level parallel processing: history, overview, and perspective?, The Journal of Supercomputing - Special issue on instruction-level parallelism, Volume 7 Issue 1-2, May 1993 (Also published by Kluwer Academic Publishers Hingham, MA, USA); ?Very Long Instruction Word architectures and the ELI-512?, ISCA '83, Proceedings of the 10th annual international symposium on Computer architecture, Pages 140-150, ACM, New York, NY, USA. Retrospective, 25 Years of ISCA, ACM, 1998; with John R. Ellis, John C. Ruttenberg and Alexandru Nicolau, ?Parallel Processing: A Smart Compiler and a Dumb Machine? Symp. Compiler Construction, 1984: 37-47. Retrospective, Best of PLDI, ACM SIGPLAN Notices, 39(4):112, 2003; and with Paolo Farabochi and Cliff Young: ?Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools?, Elsevier/Morgan Kaufmann, 2004. He is actively involved in the organization of conferences in the Computer Architecture field. In addition to serving for various program committees, he was general co-chair for ISCA-22 in Santa Margherita, Ligure, Italy in 1995; and program co-chair for MICRO-34 in Austin, Texas in 2001.