Professor Josep Torrellas

A Professor and Willett Faculty Scholar in the Department of Computer Science and a research faculty member for the Universal Parallel Computing Research Center at the University of Illinois at Urbana-Champaign. His research area is computer architecture, focusing on speculative multithreading, multiprocessor organization, integration of processors and memory, and architectural support for software debuggability and machine reliability. He has been involved in the Stanford DASH and the Illinois Cedar multiprocessor projects, and led the Illinois Aggressive COMA and FlexRAM Intelligent Memory projects. Cache Only Memory Architecture (COMA) is a computer memory organization for use in multiprocessors in which the local memories (typically DRAM) at each node are used as cache. This is in contrast to using the local memories as actual main memory, as in NUMA organizations. He has contributed to many NSF, DARPA and DOE funding initiatives. The Aggressive COMA research project was selected as one of the "Eight Point-Design Studies" that DARPA, NSF, NSA and NASA supported in the mid-nineties in a nationwide effort to accelerate the arrival of a petascale machine. He has received as lead PI several multi-million dollar NSF grants, and is the lead PI of two medium ITR grants. He has directed projects in several DARPA initiatives, including the recent "Polymorphous Computer Architectures" (PCA), and "High Productivity Computing Systems" (HPCS). In the HPCS program, he is playing a leading role in helping define the architecture of IBM's PERCS multiprocessor (POWER7). He is also involved in DOE's Extreme Scale Computation initiative. He has been at the University of Illinois since receiving his Ph.D. in Electrical Engineering from Stanford University in 1992. He also spent a sabbatical year as Research Staff Member at IBM's T.J. Watson Research Center. His current research projects are The Bulk Multicore Architecture for parallel programming productivity, and The Thrifty-Runnemede Extreme Scale Architecture. The Bulk architecture uses a novel execution model based on continuous execution of atomic blocks that enables a friendly environment for program development and debugging. The Thrifty-Runnemede architecture is designed from the ground up for energy and power efficiency. He is an IEEE and ACM Fellow and member of the National Computational Science Alliance (NCSA) and the DOE Illinois Center for the Simulation of Advanced Rockets (CSAR). He is currently the Chairman of IEEE Technical Committee on Computer Architecture (TCCA), an Associate Editor of the ACM Transactions on Architecture and Code Optimization (TACO), and a Member of the Advisory Board of the ECE Department, University of Rochester. He previously served as Vice-Chairman and Member of the Advisory Board of IEEE TCCA from 1998 to 2005. He has received an NSF Young Investigator Award, an NSF RIA, and an IBM Partnership Award. He is also the recipient of the EEE Computer Society 2015 Technical Achievement Award, for "Pioneering contributions to shared-memory multiprocessor architectures and thread-level speculation." He has published over 200 publications, many in the most competitive venues, and received 12 Best Paper awards. As of 2014, he has graduated 35 Ph.D. students, who are now leaders in academia and industry.