Hitachi SR2201

The HITACHI SR2201 was a distributed memory parallel system that was introduced in March 1996 by Hitachi. Its processor, the 150 MHz HARP-1E based on the PA-RISC 1.1 architecture, solved the cache miss penalty by pseudo vector processing (PVP). In PVP, data was loaded by prefetching to a special register bank, bypassing the cache. Each processor had a peak performance of 300 MFLOPS, giving the SR2201 a peak performance of 600 GFLOPS. Up to 2048 RISC processors could be connected via a high-speed three dimensional crossbar network, which was able to transfer data at 300 MB/s over each link.