Dr. Balaram Sinharoy

Well-known as one of the world?s top processor architects, he has been named an IBM Fellow, the company?s highest technical distinction. Among the technologies he has pioneered are simultaneous multi-threading and power-efficient, high performance, multi-core server design. He is currently chief architect of IBM?s next generation POWER technology, responsible for micro-architecture and differentiation features. He was also chief architect of IBM?s POWER7 processor, on which the Watson computer runs. The first IBM Fellow from the Bengal region of India, he is a native of Calcutta, India, and came to the United States to attend graduate school. He has been one of the main minds behind the design of the POWER microprocessor, the technology that has propelled IBM's huge gains in market share in the competitive Unix space. He earned his M.S. degree in 1988 and his Ph.D. in Computer Science in 1992 from Rensselaer Polytechnic Institute; and with more than 80 patents to his credit, he proved early in his career to be a deep, and prescient thinker. In the mid 1990?s, the microprocessor industry was at a crossroad. Within the industry and IBM, there was vigorous debate on what architecture to invest in. He is quoted as saying, ?I evaluated the VLIW (Very Long Instruction Word) processor technology and recommended that this should not be the strategic direction for IBM's server business. Intel made the decision to go in that direction. We decided not to follow Intel. In retrospect, it was the right decision.? Following that, he joined the original POWER4 processor design team and developed some of the underlying algorithms that were instrumental in making the POWER4 the highest-frequency, highest-performing processor in the industry, reaching a record of one million transactions per minute in the largest system. Some of those algorithms have remained a base component of subsequent generations of the industry-leading processor, including POWER7 which was released in 2010, and was a major evolution from the POWER6 design. He and his team devised a chip that can run 32 simultaneous tasks?with eight cores and four threads per core?delivering more than four times the performance of the previous generation processor chip, while consuming the same power. A single POWER7 chip is capable of processing more than a million transactions per minute?as powerful as the largest POWER4 system built with 32 processor chips. He splits his time between IBM offices in Poughkeepsie, N.Y., and Austin, TX.