Dr. Joel S. Emer

A pioneer in computer performance analysis techniques and a microprocessor architect. He is currently a researcher at Nvidia Corporation, an American worldwide technology company based in Santa Clara, California. He has made research contributions in simultaneous multithreading, processor pipeline organization, cache design, memory dependence prediction, performance modeling methodologies, analysis of the architectural impact of soft errors and early contributions to the now pervasive quantitative approach to processor evaluation. His current research interests include memory hierarchy design, processor reliability, reconfigurable logic-based computation and performance modeling. Born in Chicago, Illinois, he received a Bachelor's degree with highest honors in 1974, and his Master's degree in 1975 - both in Electrical Engineering from Purdue University. In 1979, he earned his Ph.D. in Electrical Engineering from the University of Illinois, Urbana-Champaign under the supervision of Professor Edward S. Davidson. After graduation he joined Digital Equipment Corporation (DEC) where he spent 22 years, initially working on VAX performance evaluation and then on Alpha performance evaluation. During his time there, DEC was acquired in June 1998 by Compaq. Some parts of DEC, notably the compiler business and the Hudson, Massachusetts facility, were sold to Intel where he became Director of Microarchitecture Research. As a consequence of his performance evaluation work, he became a pioneer in the quantitative approach to computer architecture, a set of disciplines that describes the functionality, the organization and the implementation of computer systems. In conjunction with the development and application of various performance analysis techniques, he contributed a variety of research and advanced development ideas that were incorporated into various VAX and Alpha designs. During a three year sabbatical at The Massachusetts Institute of Technology (MIT) in Cambridge, Massachusetts, he researched heterogeneous distributed systems and networked file systems. He was also a Professor of the Practice in the MIT Computer Science and Electrical Engineering department. He is well known, along with his co-author Douglas W. Clark, for a seminal paper on the quantitative analysis of processor architectures, which was published in the 11th International Symposium on Computer Architecture. That paper also contained the result that the VAX-11/780's performance was actually 0.5 MIPS instead of 1 MIPS as was previously claimed by DEC. That result helped popularize what Clark called the Iron Law of Performance that related cycles per instruction (CPI), frequency and number of instructions to computer performance. He has also contributed to simultaneous multithreading (SMT), memory dependence prediction via store sets, soft error analysis, and led the development of the Asim simulator. He was an Intel Fellow. He was also the 2009 recipient of the Eckert?Mauchly Award, an ACM/IEEE joint award for contributions to computer and digital systems architecture. He holds over 25 patents and has published more than 35 papers.